Random access memory (RAM) in the form of memory cards have been used with computers. Typically, a memory card will be populated by several integrated circuit (IC) chips, each chip being a random access memory unit. In the past, the random access memory integrated circuits were generally either dynamic random access memory (DRAM) or static random access memory (SRAM). Both DRAM and SRAM are well known in the art to be forms of volatile memory. DRAM and SRAM have a relatively fast access time when compared to non-volatile memory devices such as a hard drive.
Frequently, when the memory card is populated by the memory chips, the chips are soldered into place on a printed circuit board (PCB) of the memory card. During the soldering process, an integrated circuit chip can be damaged. Also, one or more of the soldered connections may be defective. There are basically two types of defective soldered connections. In the first type, an open condition occurs such that there is no electrical connection from a pin of the integrated circuit chip to the board. In the second type of solder defect, a short exists such that two or more pins are connected together electrically. If an integrated circuit has been damaged, or a solder defect has occurred, the memory card will not function properly. Therefore, it is desirable to have a method to test the connectivity of each pin of an integrated circuit to the memory bard. Such a test is commonly called a boundary scan test because the pins of the integrated circuit form the boundary of the circuit through which the integrated circuit interfaces with the memory card.
In the case of DRAM and SRAM, a boundary scan can be performed quickly using a programmable tester and testing methods that are well known in the art. In a typical boundary scan test, the memory card is inserted into a testing unit. The testing unit sets all of the memory units to a known state; for example, storing all zeros or all ones. Next, the tester will pick an area of interest on one of the memory units and write a pattern to that area of into;rest. The tester then reads the area of interest to compare the pattern written to the pattern read. If the pattern written does not match the pattern read, then a first type of defect has been found. The tester then reads all other areas of the memory unit, and of the other memory units, to see if the known state of these areas has changed. If the known state has changed, then a second type of defect has been found. The tester then writes another pattern to the area of interest. Typically, the first pattern will be a checkerboard pattern (e.g. 010101...) and the second pattern will be a complement checkerboard pattern (e.g. 101010...). The second pattern is then read back and compared to verify that the second pattern was stored properly. All of the other areas of the memory unit and the other memory units are again checked to verify that storing the second pattern has not changed the known state of these areas. Once the first area of interest of the first chip has been tested, a new area of interest is selected and the test process outlined above is repeated until the entire first chip has been tested. Each of the other chips of the card are also tested in a similar manner.
The above test procedure works well so long as the integrated circuit chips of the memory board being tested are SRAM or DRAM. This is because SRAM and DRAM chips may be read from, and written to, quickly. Memory cards have recently begun to be developed, however, that use flash memory integrated circuit chips rather than SRAM or DRAM. Like SRAM and DRAM, flash memory is a random access memory that can be read from quickly. Flash memory is non-volatile, however. Therefore, unlike SRAM and DRAM, flash memory retains the data stored within it after power has been removed from the memory. Also, unlike SRAM and DRAM, writing to, or clearing, flash memory takes a relatively long amount of time. This is because the flash memory must be programmed through a series of write cycles in order to achieve non-volatility.
Performing a traditional boundary scan test on a memory card that is populated with flash memory chips takes a relatively long time because of the need to perform many time consuming writes to the chip and also to perform many time consuming clearing operations. An alternative way to perform a boundary scan on a memory card populated with flash memory chips would be to add JTAG boundary scan pins and circuitry to each chip. A JTAG boundary scan is well known in the art. In a JTAG scan, test circuitry and five extra (JTAG) pins are added to each chip. The JTAG pins for each chip are then connected in series, and a series of commands are issued through the pins to the test circuitry on-board the chips to read back data and verify that the interconnections have been properly made. Details of the JTAG boundary scan may be found in the IEEE 1149.1 standard (IEEE Press, 1991).
JTAG boundary scan testing is commonly used to test chips such as microprocessors. To perform a JTAG test, however, one must add five extra pins and additional circuitry to the integrated circuit chip to be tested. Adding extra pins and circuitry required for a JTAG boundary scan is not acceptable in the case of integrated circuit memory chips. This is because to add JTAG would unacceptably increase the complexity and cost of the memory chips. For example, a memory chip typically has on the order of 50 pins, therefore, the addition of five JTAG pins would increase the number of pins for the chip by approximately 10 per cent.